root@(none):/# cat proc/version
Linux version 2.6.36.1 (root@debian_sup) (gcc version 4.3.2 (Debian 4.3.2-1.1) ) #23 Fri Feb 10 14:21:12 MSK 2012

root@(none):/# echo Test > /dev/ttyS5
-bash: echo: write error: Input/output error

root@(none):/# setserial -g /dev/ttyS*
/dev/ttyS0, UART: 16550A, Port: 0x03f8, IRQ: 4
/dev/ttyS1, UART: 16550A, Port: 0x02f8, IRQ: 3
/dev/ttyS2, UART: 16550A, Port: 0x03e8, IRQ: 15
/dev/ttyS3, UART: 16550A, Port: 0x02e8, IRQ: 15
/dev/ttyS4, UART: unknown, Port: 0x0000, IRQ: 0
/dev/ttyS5, UART: 16550A, Port: 0x0100, IRQ: 11
/dev/ttyS6, UART: 16550A, Port: 0x0108, IRQ: 11
/dev/ttyS7, UART: 16550A, Port: 0x0110, IRQ: 11
/dev/ttyS8, UART: 16550A, Port: 0x0118, IRQ: 11
/dev/ttyS9, UART: unknown, Port: 0x0000, IRQ: 0

SB Register Offset: 93h – 90h Chip Select 0 Base Address Register
31-1       BA           Chip Select 0 starts at the base address. Chip Select 0 Base Address A[31:1]. I/O map only uses A[15:1]; others are reserved.
0             EN          Chip Select 0 Base Address is enabled when set
SB Register Offset: 97h – 94h Chip Select 0 Base Address Mask
31-28     Rvd         Reserved
27           RD          ISA IOR or MEMR enabled when set
26           WR         ISA IOW or MEMW enabled when set
25           B16        0: 8-bit
1: 16-bit
24           MIO         0: I/O map
1: Memory maps I/O
23-1       BAM        Chip Select 0 Base Address Mask bit [31:9] when MIO=1(Memory maps IO). Chip Select 0 Base Address Mask bit [15:1] when MIO-0 (I/O map)  1 is compare with base address, 0 is not compare with base address.
0             Rsvd      Reserved. All are ‘0’s. To write any value to these bits causes no effect.

SB Register Offset: 9Bh – 98h Chip Select 1 Base Address Register
31-1       BA           Chip Select 1 starts at the base address. Chip Select 1 Base Address A[31:1]. I/O map only uses A[15:1]; others are reserved.
0             EN          Chip Select 1 Base Address is enabled when set
SB Register Offset: 9Fh – 9Ch Chip Select 1 Base Address Mask
31-28     Rvd         Reserved
27           RD          ISA IOR or MEMR enabled when set
26           WR         ISA IOW or MEMW enabled when set
25           B16        0: 8-bit
1: 16-bit
24           MIO         0: I/O map
1: Memory maps I/O
23-1       BAM        Chip Select 1 Base Address Mask bit [31:9] when MIO=1(Memory maps IO). Chip Select 1 Base Address Mask bit [15:1] when MIO-0 (I/O map)  1 is compare with base address, 0 is not compare with base address.
0             Rsvd      Reserved. All are ‘0’s. To write any value to these bits causes no effect.

SB Register Offset: 47h – 44h ( Bit 19-18 ) ISA GPCS 0/1 Driving Current Control
00: 4mA
01: 8mA (default)
10: 12mA
11: 16mA